A new less memory intensive net model for timing-driven analytical placement

We introduce a new hybrid net model for timing-driven analytical placement. This new hybrid net model decreases the average critical path delay obtained after global placement with 14% compared to wire-length-driven analytical placement. The obtained HPWL (Half Perimeter Wire-Length) remains the same. This is a very interesting feature of the hybrid net model. We also introduce a new gradual legalization method which leads to a decrease in the obtained HPWL after global placement of 2% on average and up to 23% for some individual benchmark circuits compared to the traditional recursive partitioning based complete legalization algorithm. Although some previous work about analytical placement on FPGAs has already been published, none of these publications have resulted in the release of a publicly available analytical FPGA placement framework. Also, there are very few implementation details available in the existing publications done about this subject. We will release our code as an open source project. In this way we hope to encourage the academic research efforts done on analytical placement algorithms for FPGAs.